1. Field of the Invention
The invention relates to the Extended Industry Standard Architecture (EISA) for computer systems, and more particularly, to the execution of a hidden refresh on local memory when an EISA-defined refresh takes place on the system bus.
2. Description of Related Art
The IBM PC AT computer architecture has become industry standard architecture for personal computers, and is typically built around a CPU such as an 80286, 80386 or 80486 microprocessor manufactured by Intel Corporation. The CPU is coupled to a host or local bus, capable of performing memory accesses and data transfers at high rates of speed (i.e., on the order of 10-50 MHz). The host bus includes 16 or 32 data lines, a plurality of address lines, and various control lines. The typical IBM PC AT-compatible platform also includes DRAM main memory, and in many cases cache memory, both coupled to the local bus.
The typical IBM PC AT-compatible computer also includes a system bus which is separate and distinct from the local bus. The system bus is coupled to the host bus via certain interface circuitry. The system bus includes 8, 16 or 32 data lines, a plurality of address lines, as well as control lines. The system bus historically was addressed by the CPU in the CPU's I/O address space rather than its memory address space. The I/O address space is logically distinct from the memory address space and if the CPU desires to access an I/O address, it does so by activating an MIO# signal on the host bus to indicate that this is an access to the I/O address space. The interface circuitry recognizes the I/O signals thereby generated by the CPU, performs the desired operation over the system bus, and if appropriate, returns results to the CPU over the host bus.
In practice, some I/O addresses may reside physically on the host bus and some memory addresses may reside physically on the system bus. The interface circuitry is responsible for recognizing that a memory or I/O address access must be emulated by an access to the other bus, and is responsible for doing such emulation.
In addition to the above elements, a typical IBM PC AT-compatible system includes a DMA controller which permits peripheral devices on the system bus to read or write directly to or from local memory, as well as an interrupt controller for transmitting interrupts from various add-on cards to the CPU. The add-on cards are cards which may be plugged into slot connectors coupled to the system bus to increase the capabilities of the system.
General information on the various forms of IBM PC AT-compatible computers can be found in IBM, "PC/AT Technical Reference Manual", in Sanchez, "IBM Microcomputers: A Programmer's Handbook" (McGraw-Hill: 1990) and Solari, "AT Bus Design" (San Diego: Annabooks, 1990). See also the various data books and data sheets published by Intel Corporation concerning the structure and use of the iAPX-86 family of microprocessors, including the "i486 Microprocessor Hardware Reference Manual", published by Intel Corporation, copyright date 1990, "386 SX Microprocessor", data sheet, published by Intel Corporation (1990), and "386 DX Microprocessor", data sheet, published by Intel Corporation (1990). All the above references are incorporated herein by reference.
The original IBM PC-AT computer architecture has spawned several architectural variations which themselves have become standards in the microcomputer industry. These standards include ISA ("Industry Standard Architecture") and EISA ("Extended Industry Standard Architecture"). The EISA architecture is intended to be upward compatible from the ISA architecture, meaning that an add-on card built for ISA should work properly if used in an EISA computer.
The host bus in the various PC-AT compatible architectures includes a plurality of address lines and a plurality of data lines, as well as a number of control lines and power and ground. The exact set of lines which make up the host bus is well known in the industry, and may be determined from various sources, including the references cited above. For present purposes, it is sufficient to identify the following signal lines on the local bus ("#" indicates active low):
______________________________________ HA(23:1) or Address lines. For the 80286 and 80386SX, HA(31:2) 24 bits of address are provided. The high order 23 bits are provided on HA(23:1). For the 80386DX and 80486, 32 bits of address are available. The high order 30 bits are provided on HA(31:2). HBHE# & Host Byte High Enable and Host Byte Low HBLE# or Enable, or Host Byte Enables (3:0). For the HBE#(3:0) 80286 and 80386SX, HBLE# can be thought of as equivalent to HA(0) and HBHE# = IBLE#. For the 80386DX and 80486, HBE#(3:0) carries a 1-of-4 decode of the 2 low order address bits. HD(15:0) or Data lines. The 80286 and 80386SX operate HD(31:0) with a 16-bit external data bus, and the 80386DX and 80486 operate with a 32-bit data bus. M/IO# Memory/IO control line. When asserted low by the CPU, indicates that the address on HA is an I/O address as opposed to a main memory address. RDY# Acknowledgment to CPU that a current request has been serviced and CPU can start a new cycle. RDY# always terminates the current cycle, even if it is asserted in the middle of a burst cycle (486 processors only). BRDY# (486 Analogous to RDY# except that it does not processors) terminate a burst cycle in progress. CPU responds to BRDY# by expecting the next clock cycle to be another data transfer. Up to 16 bytes (in four double words) can be transferred during a burst. The CPU asserts BLAST# to end the burst. BLAST# (486 CPU asserts BLAST# to indicate that the processors) next BRDY# returned to CPU will be the last in the cycle, whether burst or not. BRDY# wkh BLAST# asserted has the same effect as RDY#. CLK2, CLK CPU clock signal. or HCLK W/R# Distinguishes host write cycles from host read cycles. D/C# Distinguishes host data cycles, either memory or I/O, from host control cycles which are: interrupt acknowledge, halt, and instruction fetching. HADS# Indicates that a valid bus cycle definition and address (W/R#, D/C#, M/IO#, HBE0#, HBE1#, HBE2#, HBE3# (or HBHE# and HBLE#) and HA) are being driven on the host bus. HADS# is asserted synchronously with a rising edge of CLK and both sampled and withdrawn synchronously with the next rising edge of CLK. HOLD Bus hold request. Allows another bus master complete control of the CPU bus. In response to HOLD going active the CPU will float most of its output and input/output pins. HLDA will be asserted after completing the current bus cycle, burst cycle or sequence of locked cycles. The CPU will remain in this state until HOLD is de- asserted. HLDA Hold acknowledge. Goes active in response to a hold request presented on the HOLD signal pin. HLDA indicates that the CPU has given the bus to another local bus master. HLDA is driven active in the same clock that the CPU floats its bus. HLDA is driven inactive when leaving bus hold. HLDA is active HIGH and remains driven during bus hold. BOFF# Backoff. When this CPU input signal is asserted, the CPU aborts any cycle currently in progress and floats most of its output and input/output pins (the same pins as those floated during HLDA). The pins remain floated until BOFF# is de-asserted, at which time the CPU restarts any aborted cycle. BREQ# (486 CPU output indicates that it needs access to processors) CPU bus, or that it is currently using the bus. Used by external logic for arbitration purposes. BREQ is always generated when the processor has a cycle pending, whether or not it is currently driving the bus. It may be asserted during a bus hold (HOLD), bus backoff (BOFF# ), or address hold (AHOLD#). After HLDA, the CPU continues executing from its internal cache if it can. Only when it next requires access to the CPU bus does it assert BREQ#. ______________________________________
The various signals on an EISA system bus are also well specified and well known in the industry. They are described in BCPR Services, Inc., "EISA Specification", ver. 3.11 (1990). For present purposes, only the following signals are important:
______________________________________ SA(19:0) 20 address lines. Sufficient to address 1 MB of memory. Only SA(15:0) are used to address the 64k I/O address space, and only SA(9:0) are used to address the basic 1k AT I/O address space. LA(31:2) Additional address lines for addressing a 16MB memory address space on the I/O bus. The LA lines are valid earlier in an I/O bus cycle, but must be latched if needed later in the cycle. The SA lines are not valid as early as the LA lines, but remain valid longer. SD(31:0) 32 data lines. BCLK I/O bus clock signal. 6-8.33 MHz signal. Usually a square wave, but the EISA standard specification states that a BCLK cycle can be stretched in certain situations in order to ensure that a desired edge of an EISA bus signal occurs synchronously with a desired edge of BCLK. START# Start a bus cycle. Interface chipset or EISA master activates START# when the address lines LA(31:2) and M/IO are valid. START# terminates in response to the rising edge of BCLK which occurs at least one full BCLK cycle after it was asserted. Sampled on the rising edge of BCLK if necessary. REFRESH# Indicates that either the system board refresh controller or an external ISA master is performing a refresh cycle on the system bus. DRQ#(7:5,3:0) Used to request DMA service by a DMA device or an ISA master to gain control of the system bus. Remains active until the last transfer has been started on the system bus. DAK#(7:5,3:0) Indicate that a request by a DMA device or an ISA master for control of the system bus has been granted. For ISA masters and ISA compatible DMA devices, DAK# remains active until the last transfer has been completed. For EISA devices performing an enhanced DMA, the DAK# trailing edge can occur earlier to indicate a request for bus preemption. MRQ#(5:0) Used by an EISA master to request control of the system bus. Remains active until the last transfer has been started on the system bus. MAK#(5:0) Indicate that a request by an EISA master for control of the system bus has been granted. The MAK# trailing edge can occur before the last transfer has been completed to indicate a request for preemption. CMD# Indicates when data is valid on the SD lines for write cycles. The leading (falling) edge of CMD# must be synchronous with a rising edge of BCLK and occurs at the same time as the trailing edge of START#. It remains active until the end of the cycle and usually, but not always, terminates synchronously with a rising edge of BCLK. MSBURST# Master Burst. Asserted by an EISA bus master if both the master and the slave are capable of supporting the next cycle as a burst cycle. Sampled on rising edge of BCLK. EXRDY EISA Ready. De-asserted by an EISA slave when it is not ready to terminate an EISA cycle. Sampled on the falling edge of BCLK after CMD# becomes active. If EXRDY is inactive at that time, EXRDY is sampled again on each BCLK failing edge thereafter. CMD# remains active for at least one-half of a BCLK cycle after EXRDY is sampled active, so this signal is useful for generating an "early ready" signal to the CPU. CHRDY ISA Channel Ready. De-asserted by an ISA slave before a falling edge of BCLK if the slave will not be ready to terminate an ISA cycle on the next BCLK rising edge. Sampled on the falling edge of BCLK just prior to the BCLK rising edge on which the ISA cycle would otherwise terminate. If CHRDY is low at that time, it is sampled again on each BCLK falling edge thereafter. CMD# remains active for at least one-half BCLK cycle after CHRDY is sampled active, so like EXRDY, CHRDY is useful for logic which generates an "early ready" signal to the CPU. NOWS# ISA No Wait State slave. Asserted by an ISA slave before a BCLK falling edge to shorten default-length ISA cycles. Sampled on BCLK falling edge and if active at that time, will cause CMD# to go inactive on the immediately following BCLK rising edge. If CHRDY is low at the time NOWS# is sampled active, termination of the cycle is delayed. CMD# will remain active for at least one-half BCLK cycle after NOWS# is sampled active, and so NOWS# can be used in logic to generate an "early ready" signal to the CPU. ______________________________________
Recently, efforts have been made to reduce the size and improve the manufacturability of PC AT-compatible computers. Specifically, several manufacturers have developed "PC AT chipsets", which integrate a large amount of the system interface circuitry and other circuitry onto only a few chips. An example of such a chipset for ISA microcomputers is the 386WB PC/AT chipset manufactured by OPTi, Inc., Santa Clara, Calif. Examples of such a chipset for EISA microcomputers are described in Intel, "82350 EISA Chip Set" (1990) and in Intel, "82350DT EISA Chip Set" (1992), both available from Intel Corp., Santa Clara, Calif., and incorporated by reference herein. Another example of such a chipset for EISA microcomputers is described in Buchanan, "A Highly Integrated VLSI Chip Set For EISA System Design", Silicon Valley Personal Computer Design Conference Proceedings, Jul. 9-10, 1991, pp. 293-306.
In an EISA-based system, several resources are typically made shareable among various masters. The resources include the system bus, the host bus, and local memory. The EISA standard specifies an arbitration priority for access to the system bus, but leaves it to the designer to determine how and when a device may control the host bus and/or the local memory. In particular, the EISA specification provides for centralized arbitration control to allow sharing of the EISA bus among three groups of requestors, including (1) the CPU or an EISA device; (2) an ISA device or DMA controller; and (3) a refresh controller. A device desiring access to the EISA bus asserts a bus request signal to the centralized arbitration controller, which arbitrates the request and asserts a bus grant signal when the bus is available. Other devices may preempt an active device by asserting a bus request to the centralized arbitration controller, which then negates the then-active bus grant signal to indicate to the active device that it must release the bus. After the active device releases the bus and so indicates by de-asserting its bus request signal, the centralized arbitration controller will assert the appropriate bus grant signal for the next winning device. The EISA specification specifies the maximum delay which the active device may take after its bus grant signal is negated, before the arbitration controller will force it off the bus.
The EISA specification calls for a multi-level rotating arbitration priority. The arbitration scheme gives DMA channels a high level of priority to assure compatibility with traditional ISA add-on cards which can tolerate only a short bus latency. EISA devices have a lower priority and their design must provide for longer latency. The arbitration scheme gives the system bus to the CPU by default when no other device is requesting use of the bus. In addition, the CPU may request EISA bus access when it has a cycle to execute.
FIG. 1 shows the rotating priority scheme prescribed by the EISA standard for devices desiring access to the EISA bus. The top priority level as defined in the EISA specification, as indicated in box 102, uses a three-way rotation to grant bus access sequentially to a refresh controller indicated by box 104, either the CPU or an EISA device as indicated in box 106, and a DMA/ISA device as indicated in box 108. One device from each of the three groups will gain access to the EISA bus at least once in every three arbitration cycles, depending on which devices are requesting service. A device that does not request the EISA bus is skipped in the rotation.
When the centralized arbitration controller grants the bus to the CPU or EISA device as indicated in box 106, the bus is granted to the CPU or an EISA device in a second-level two-way rotation, as indicated in box 110. Further, when an EISA device is granted control of the bus, the particular EISA device chosen is selected according to a third-level six-way rotation of EISA devices as indicated in box 112. If the central arbitration controller grants the EISA bus to a DMA/ISA device at the top level, as indicated in box 108, the particular channel which receives the bus is selected either according to strict numeric priority, as indicated in box 114, or according to a cascaded rotating priority scheme as indicated in boxes 116 and 118. The user of the system programs which scheme is to be used for the DMA/ISA device. If the cascaded rotating priority scheme is chosen, then the selection rotates among channels 5, 6, 7 and a cascade channel (box 116), which when selected rotates among channels 0, 1, 2 and 3 (box 118). Once a DMA/ISA device is selected at the top level of the EISA rotation priority 102, arbitration for the particular channel, as indicated in boxes 114, 116 and 118, is the same as the arbitration scheme for the prior ISA-based computer systems.
One EISA chipset which maintains the EISA priority arbitration sequence for access to the EISA bus is the 82350 chipset manufactured by Intel Corporation, This chipset is described in Intel, "82350 EISA Chipset" (1990), incorporated herein by reference. The central arbitration controller of the 82350 chipset grants access to the EISA bus, the host bus and the local DRAM, all as a single resource. That is, when an EISA device, the refresh controller or a DMA/ISA device wins the arbitration, the chipset issues a HOLD request to the CPU. Only when the CPU acknowledges the HOLD request and responds with an HLDA, does the chipset return a bus grant signal to the winning device. The CPU may continue executing out of cache (depending on the cache design) while the winning device controls the remainder of the system, but cannot perform any cycles to local memory even if the winning device can perform its desired operation entirely on the system bus.
The 82350 scheme is particularly problematical if the winner of the EISA arbitration is the refresh controller. A refresh cycle on the EISA is lengthy by definition, requiring four cycles of a 120 nS bus clock (BCLK) plus arbitration overhead. The CPU cannot access local DRAM or external cache during this period. Such a delay can significantly affect CPU throughput.
A chipset which reduces this problem is the 82350DT chipset, also manufactured by Intel Corporation. The chipset is described in Intel, "82350DT EISA Chipset" (1992), incorporated herein by reference. The 82350DT chipset is a complicated arrangement which can operate either in a concurrent mode or a non-concurrent mode, selectably by the user, and in the concurrent mode can operate with a coupled or decoupled refresh of local DRAM, also selectably by the user. In the non-concurrent mode, as in the 82350 chipset, the CPU is held during the time that a device winning the EISA arbitration is granted access to the EISA bus. In concurrent mode, the CPU is not held when another device is granted control of the EISA bus. Instead, an 82359 memory controller monitors the EISA bus address lines and arbitrates for control of the local DRAM only when the device that won the EISA arbitration actually requires the local DRAM. In this way, the 82359 memory controller simulates dual port access (one port receiving the host bus address and one port receiving the EISA bus address) to local DRAM.
If the winning device is the EISA refresh controller, (or if an ISA device asserts REFRESH#), the EISA bus REFRESH# signal will go low. In either the concurrent on non-concurrent modes, when the 82359 operates in coupled refresh mode, the 82359 monitors the EISA bus REFRESH# to perform a local DRAM refresh cycle at the same time that refresh is executed on the EISA bus. When REFRESH# goes active, the 82359 arbitrates for ownership of the local memory, and when obtained, performs the local DRAM refresh using its own internally generated refresh address. The 82359 pulls the EISA bus EXRDY signal low until the local DRAM refresh completes, to prevent any new cycle from beginning.
Accordingly, in concurrent, coupled refresh mode, the CPU is never held when a device other than the CPU wins the EISA arbitration. When the CPU needs access to the local DRAM or system bus for reading or writing, the CPU has to wait until the refresh cycle on the system bus and the local DRAM are complete. Also, the refresh cycle on the system bus is extended (by de-asserting EXRDY) until the slower local DRAM refresh completes. This causes a further delay for any pending EISA/ISA/DMA master cycles as well as any CPU cycles to local DRAM or the system bus.
In concurrent, decoupled refresh mode, the 82359 ignores the REFRESH# signal on the system bus. Instead it uses an internal refresh timer which arbitrates local DRAM away from the current owner when a local DRAM refresh is needed. It uses a RAS# only refresh scheme which is faster than the system bus refresh and approximately as fast as a CAS# before RAS# refresh. This minimizes the delay for any pending EISA/ISA/DMA master cycle to host memory, and any CPU cycle to local DRAM or the system bus. However, concurrent decoupled refresh mode can not be used in the 82350DT chipset when an ordinary, single-ported, cache controller is connected to the host bus.
Many DRAMs support a fast "CAS# before RAS# refresh" function. In a CAS# before RAS# refresh, external circuitry merely activates the CAS# line before the RAS# line. No address need be provided. Neither the 82350 nor the 82350DT chipset takes advantage of fast CAS# before RAS# refresh capability of many DRAMs. Certain ISA chipsets, however, such as the OPTi 386WB chipset, do. In the ISA priority arbitration sequence, the CPU has the lowest priority and DMA/ISA devices share the highest priority with the refresh controller on a first-come, first-served basis. In the 386WB chipset, if a DMA/ISA device wins the arbitration, the chipset asserts DHOLD to the CPU and when the CPU responds with DHLDA, the chipset grants control of all three systems resources (ISA bus, CPU bus and local memory) to the winning DMA/ISA device. If the refresh controller wins the arbitration, however, then the CPU is not held. Instead, a refresh cycle is performed on the ISA bus only. The DRAM controller monitors the ISA refresh line and, in response to a falling (leading) edge, performs a CAS# before RAS# refresh of the local DRAM. The DRAM controller delays BRDY# to the CPU if a CPU to DRAM cycle must be delayed. The EBC delays RDY# to the CPU if a CPU to system bus cycle is delayed because of the refresh taking place on the ISA bus. The CPU can continue to access external cache during the entire refresh cycle, and need not wait long for access to local DRAM since the local DRAM refresh is faster than the system bus refresh.
However, avoiding the cost of a dual-ported DRAM controller and simply following the former ISA priority arbitration sequence would violate the EISA arbitration sequence and thereby risk incompatibility with newly developed EISA hardware.